Method of fabricating semiconductor device and semiconductor device fabricated by the method

ABSTRACT

A method of fabricating a semiconductor device includes forming a first polycrystalline silicon layer on a gate insulating film so that a vertically intermediate portion has a higher dopant concentration than vertically upper and lower portions, forming a second polycrystalline silicon layer on an intergate insulating film so that a vertically intermediate portion has a higher dopant concentration than vertically upper and lower portions, executing a thermal oxidation treatment for the polycrystalline silicon layers with side surfaces of gate electrodes being exposed, thereby forming a silicon oxide film, selectively removing the silicon oxide film by an etch with use of a chemical solution, thereby forming recesses in side surfaces of the first and second polycrystalline silicon layers respectively, and burying insulating films between the gate electrodes respectively and forming air gaps in portions of the buried insulating films corresponding to the recesses respectively.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims the benefit of priority from theprior Japanese Patent Application No. 2008-151625, filed on Jun. 10,2008, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating a semiconductordevice which is configured to have an air gap defined between adjacentmemory cells, and the semiconductor device fabricated by the method.

2. Description of the Related Art

A flash memory can maintain stored data even without power supplythereto and have accordingly been widely used as a memory element for amultimedia card. The memory capacity of the flash memory has recentlybeen desired to be increased. For this purpose, high integration ofmemory cells is further necessitated. Technical problems posed by highintegration of memory cells include an increase in a capacity betweencells adjacent to each other. A silicon oxide is buried between gateelectrodes of adjacent memory cells as an insulator in an ordinarystructure of the memory element. The silicon oxide can be formed easilyand has a dielectric constant that is about half of that of a siliconnitride, so that the silicon oxide can reduce a capacity betweenadjacent memory cells. However, a capacity between adjacent memory cellsis increased in inverse proportion to a distance therebetween as aninterval of memory cells is reduced. As a result, an operating speed ofthe memory element is reduced and a malfunction (in data write and/orreadout) occurs.

In view of the above-described problem, the conventional art hassuggested a configuration in which nothing is formed between gateelectrodes of adjacent memory cells, that is, a configuration in whichan air gap with a minimum dielectric constant is defined, in order thatthe capacity between adjacent memory cells may be reduced (see Japanesepatent application publication JP-A-2007-157927). An air gap hasconventionally been formed by covering an upper part of each gateelectrode when a silicon oxide film is buried between the gateelectrodes. However, it has been difficult to form an air gapcontrollably by the conventional method.

BRIEF SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided amethod of fabricating a semiconductor device, comprising forming a gateinsulating film on a semiconductor substrate, forming a first conductivelayer, as a floating gate electrode, on the gate insulating film so thata vertically intermediate portion of the first conductive layer has ahigher dopant concentration than vertically upper and lower portions ofthe first conductive layer, forming an intergate insulating film on thefirst conductive layer, forming a second conductive layer, as a controlgate electrode, on the intergate insulating film so that a verticallyintermediate portion of the second conductive layer has a higher dopantconcentration than vertically upper and lower portions of the secondconductive layer, dividing the first and second conductive layers andthe intergate insulating film with a mask pattern formed on the secondconductive layer serving as a pattern, thereby forming a plurality ofgate electrodes, forming a first recess on a first side wall of thefirst conductive layer and a second recess on a second side wall of thesecond conductive layer with side surfaces of the gate electrodes beingexposed, and burying insulating films between the gate electrodesrespectively and forming a first and a second air gap portions inportions of the buried insulating films corresponding to the first andthe second recesses respectively.

According to another aspect of the present invention, there is provideda method of fabricating a semiconductor device, comprising forming agate insulating film on a semiconductor substrate, forming a firstconductive layer on the gate insulating film by forming a first undopedamorphous silicon layer on the gate insulating film, forming a firstamorphous silicon layer doped with phosphor on the first undopedamorphous silicon layer and forming a second undoped amorphous siliconlayer on the first amorphous silicon layer, forming an intergateinsulating film on the first conductive layer, forming a secondconductive layer on the intergate insulating film by forming a thirdundoped amorphous silicon layer on the intergate insulating film,forming a second amorphous silicon layer doped with phosphor on thethird undoped amorphous silicon layer and forming a fourth undopedamorphous silicon layer on the second amorphous silicon layer, dividingthe first and second conductive layers and the intergate insulating filmwith a mask pattern formed on the second conductive layer serving as apattern, thereby forming a plurality of gate electrodes, forming a firstrecess on a first side wall of the first conductive layer and a secondrecess on a second side wall of the second conductive layer with sidesurfaces of the gate electrodes being exposed, and burying insulatingfilms between the gate electrodes respectively and forming a first and asecond air gap portions in portions of the buried insulating filmscorresponding to the first and the second recesses respectively.

According to further another aspect of the present invention, there isprovided a semiconductor device comprising a semiconductor substrate, agate insulating film formed on an upper surface of the semiconductorsubstrate, a plurality of gate electrodes including a floating gateelectrode formed on the gate insulating film, an intergate insulatingfilm formed on the floating gate electrode, and a control gate electrodeformed on the intergate insulating film, and a plurality ofinter-electrode insulating films formed on portions of the semiconductorsubstrate located between the gate electrodes, wherein each floatinggate electrode has a pair of first vertical end portions and a firstvertically intermediate portion between the first vertical end portions,the first vertically intermediate portion has a first gate width whichis smaller than a second gate width of the first vertical end portions,and each control gate electrode has a pair of second vertical endportions and a second vertically intermediate portion between the secondvertical end portions, the second vertically intermediate portion has athird gate width which is smaller than a fourth gate width of the secondvertical end portions, and each inter-electrode insulating film has afirst air gap portion corresponding to the first vertically intermediateportions of the floating and the control gate electrodes and a secondair gap portion corresponding to the second vertically intermediateportions of the floating and the control gate electrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings,

FIG. 1 shows an electrical arrangement of a memory cell region of a NANDflash memory of a first embodiment in accordance with the presentinvention;

FIG. 2 is a schematic plan view of the memory cell region;

FIG. 3 is a schematic longitudinal side section taken along line 3-3 inFIG. 2;

FIG. 4 is a schematic longitudinal side section, showing a stage of thefabricating process (No. 1);

FIG. 5 is an enlarged schematic longitudinal side section of apolycrystalline silicon layer (amorphous silicon layer) for the formingof a control gate electrode CG;

FIG. 6 is a schematic longitudinal side section, showing another stageof the fabricating process (No. 2);

FIG. 7 is a schematic longitudinal side section, showing further anotherstage of the fabricating process (No. 3);

FIG. 8 is a schematic longitudinal side section, showing further anotherstage of the fabricating process (No. 4);

FIG. 9 is a schematic longitudinal side section, showing further anotherstage of the fabricating process (No. 5);

FIG. 10 is a schematic longitudinal side section, showing furtheranother stage of the fabricating process (No. 6); and

FIG. 11 is a schematic longitudinal side section, showing furtheranother stage of the fabricating process (No. 7).

DETAILED DESCRIPTION OF THE INVENTION

One embodiment of the present invention will be described with referenceto the accompanying drawings. The invention is applied to a NAND flashmemory in the embodiment. In the following description, identical orsimilar parts are labeled by the same reference numerals. The drawingstypically illustrate the invention, and the relationship between athickness and plane dimension, layer thickness ratio and the like differfrom respective natural dimensions.

Firstly, an electrical arrangement of the NAND flash memory 1 will bedescribed. FIG. 1 shows an equivalent circuit showing a part of memorycell array Ar of the NAND flash memory 1. The memory cell array Arincludes a number of NAND cell units (string units) Su arranged intorows and columns. Each NAND cell unit includes a plurality of or, in theembodiment, two selective gate transistors Trs1 and Trs2 and a pluralityof, for example, thirty-two (2^(n) where n is a positive integer) memorycell transistors Trm series-connected between the selective gatetransistors Trs1 and Trs2. Each source/drain region is shared by theadjacent memory cell transistors Trm in each NAND cell unit Su. Thememory cell transistors Trm arranged in the X direction in FIG. 1(corresponding to a direction of word lines or gate width) are connectedin common to word lines WL (control gate lines). Furthermore, theselective gate transistors Trs1 arranged in the X direction in FIG. 1are connected in common to selective gate lines SGL1, whereas selectivegate transistors Trs2 arranged in the X direction in FIG. 1 areconnected in common to selective gate lines SGL2.

Bit line contacts CB are connected to drain regions of the selectivegate transistors Trs1. The bit line contacts CB are connected to bitlines BL extending in the Y direction (corresponding to a direction ofgate length or the bit lines) perpendicular to the X direction inFIG. 1. Furthermore, the selective gate transistors Trs2 are connectedvia source regions to source lines SL extending in the X direction inFIG. 1.

FIG. 2 illustrates a layout pattern of a part of the memory cell region.FIG. 3 is a schematic section taken along line 3-3 in FIG. 2. Aplurality of element isolation regions Sb of a shallow trench isolation(STI) structure are formed in a silicon substrate 2 serving as asemiconductor substrate so as to extend in the Y direction as viewed inFIG. 2. The element isolation regions Sb are formed so as to be drawn upin a plurality of lines at predetermined intervals in the X direction,whereby element regions (active areas) Sa are formed so as to extend inthe Y direction and so as to be separated from each other in the Xdirection in FIG. 2.

A plurality of word lines WL are formed so as to intersect the elementregions Sa and so as to be spaced from each other in the Y direction.Furthermore, a pair of selective gate lines SGL1 of the selective gatetransistors are formed so as to extend in the X direction in FIG. 2. Thebit line contacts CB are formed on the element regions Sa between theselective gate lines SGL1. Gate electrodes MG (corresponding to stackedgate electrodes) of the memory cell transistors Trm are formed onportions of the element regions Sa intersecting the word lines WL. Gateelectrodes SG of the selective gate transistors Trs1 and Trs2 are formedon portions of the element regions Sa intersecting the selective gatelines SGL1.

FIG. 3 is a schematic section (a state during fabrication process) takenalong line 3-3 in FIG. 2, mainly showing the gate electrodes MG of thememory cell transistors Trm located on the element regions Sa and theperipheral structure. As shown, each gate electrode MG includes apolycrystalline silicon layer 4, an intergate insulating film 5 and ametal silicide layer 6 all of which are sequentially deposited on thesilicon substrate 2 with a silicon oxide film 3 being interposed betweenthe silicon substrate 2 and the polycrystalline silicon layer 4. Thesilicon oxide film 3 is formed by applying a thermal oxidation treatmentto the upper surface of a silicon substrate 2. The silicon oxide film 3serves as a gate insulating film and a tunnel insulating film. Thepolycrystalline silicon layer 4 is doped with impurities such asphosphor (P) and formed into a floating gate electrode FG. A metalsilicide layer 6 is an alloy layer that is formed so as to serve as thecontrol gate electrode CG. The metal silicide layer 6 reduces aresistance value of the word line WL. Each control gate electrode CG mayhave a double layer structure of a polycrystalline silicon layer and ametal silicide layer, although being composed of a metal silicide layer.

Each intergate insulating film 5 serves both as an insulating filmbetween the floating gate electrode FG and the control gate electrode CGand as an inter-conductive layer of the polycrystalline silicon layer 4and the metal silicide layer 6. Each intergate insulating film 5comprises, for example, a deposition of silicon oxide film-siliconnitride film-silicon oxide film (ONO). Alternatively, each intergateinsulating film 5 may comprise a high dielectric film such as alumina.Furthermore, a low-concentrated impurity diffusion layer (not shown) isformed as a source/drain region in a part of a surface layer locatedbetween the gate electrodes MG of each memory cell transistor Trm. Asilicon oxide film 7 is formed as an interelectrode insulating film onthe part of the silicon substrate 2 located between the gate electrodesMG. Furthermore, a cavity or void where nothing is formed, or an air gapis formed in a part of the silicon oxide film 7 located between the gateelectrodes MG. An interlayer insulating film (not shown) is formed onthe aforesaid silicon oxide film 7. A silicon nitride film (not shown)is formed as a barrier film on the interlayer insulating film.Furthermore, another interlayer insulating film (not shown) is formed onthe aforesaid silicon nitride film.

A method of fabricating the foregoing configuration will now bedescribed with reference to FIGS. 4 to 11. The features of theembodiment will mainly be described in the following. However, one ormore steps described in the following may be eliminated if occasiondemands, and one or more steps may be added if these steps are necessaryto form the structure of another region not shown in the drawings.

Firstly, a thermal oxidation process is applied to the silicon substrate2 so that the silicon oxide film 3 is formed, as shown in FIG. 4. Next,the polycrystalline silicon layer 4, the intergate insulating film 5 anda polycrystalline silicon layer 9 are sequentially formed by alow-pressure chemical vapor deposition (LPCVD) method. Here, thefollowing will describe a process of forming the polycrystalline siliconlayer 4 for the floating gate electrodes FG and the polycrystallinesilicon layer 9 for the control gate electrodes CG with reference toFIG. 5. Although FIG. 5 illustrates the process of forming the controlgate electrodes CG, the floating gate electrodes FG are formed by thesame process as the control gate electrodes CG. An undoped amorphoussilicon layer 9 a is firstly formed on the intergate insulating film 5so as to have a first film thickness of X nm, as shown in FIG. 5. Theundoped amorphous silicon layer 9 a is formed by causing a silane (SiH₄)gas to flow into a furnace heated at a temperature between 500 and 530°C. by an amount ranging from 200 to 1000 standard cc/min (sccm).Subsequently, a P-doped amorphous silicon layer 9 b doped with phosphor(P) is formed on the undoped amorphous silicon layer 9 a so as to have apredetermined film thickness Y nm. The P-doped amorphous silicon layer 9b is formed with supply of phosphine (PH₃) ranging from several to 200sccm under the foregoing forming condition of the undoped amorphoussilicon layer 9 a. Next, an undoped amorphous silicon layer 9 c isformed on the P-doped amorphous silicon layer 9 b so as to have apredetermined film thickness Z nm. The undoped amorphous silicon layer 9c is formed under the same forming condition as the undoped amorphoussilicon layer 9 a.

Each of the polycrystalline silicon layers 4 and 9 comprises the undopedamorphous silicon layer interposed between the upper and lower dopedamorphous silicon layers. In other words, each polycrystalline siliconlayer is composed of upper and lower layers each of which comprises theundoped amorphous silicon layer and an intermediate layer comprising theP-doped amorphous silicon layer. The amorphous silicon layers 9 a, 9 band 9 c may be formed continuously by the use of the same processingequipment or with suspension for every layer. Furthermore, the amorphoussilicon layers 9 a, 9 b and 9 c may be formed by different equipments.When the forming of each layer is suspended or carried out by aplurality of different equipments, a native oxide can be formed in aboundary between adjacent layers. As a result, uniform diffusion ofphosphor in the three layers can be suppressed when subsequent stepsinclude a high-temperature process. The film thicknesses of the layerscan be adjusted to respective desired values. The polycrystallinesilicon layer 4 for the floating gate electrodes FG also comprises anundoped amorphous silicon layer, a P-doped amorphous silicon layer andan undoped amorphous silicon layer in the same manner as thepolycrystalline silicon layer 9.

Subsequently, a silicon nitride film 10 is formed on the polycrystallinesilicon layer 9 (amorphous silicon layers 9 a, 9 b and 9 c). The siliconnitride film 10 serves as a hard mask for forming the polycrystallinesilicon layer 4 (see FIG. 6). When the temperature is excessivelyincreased in the forming of the silicon nitride film 10, there is apossibility that the dopant P may uniformly be diffused in each layer.In view of the problem, the silicon nitride film 10 is formed by aforming process at a low temperature of not more than 500° C. at whichthe dopant P cannot uniformly be diffused.

Subsequently, a resist (not shown) is applied to the silicon nitridefilm 10 to be patterned by the photolithography process. The siliconnitride film 10 is then processed by a dry etching process (a reactiveion etching (RIE) method) as shown in FIG. 6. Next, an etching process(RIE method) is carried out with the patterned silicon nitride film 10serving as a mask, whereby the deposited film for the gate electrodes MGof the memory cell transistors is formed. The deposited film comprisesthe amorphous silicon layer (polycrystalline silicon layer) 9, intergateinsulating film 5, amorphous silicon layer (polycrystalline siliconlayer) 4 and silicon oxide film 3 (see FIG. 6). Next, the resist isremoved. Alternatively, the resist may be removed immediately after theforming of the silicon nitride film 10. Additionally, the silicon oxidefilms 3 between the adjacent gate-electrode MG forming regions mayremain although removed. Each of the formed polycrystalline siliconlayers 4 and 9 has a dopant (P) concentration gradient that aconcentration of the dopant (P) has a predetermined value and becomessmaller than the predetermined value as each approaches both endsthereof.

Subsequently, a thermal oxidation process is executed while both sidesof each gate electrode MG (sides of each word line) are exposed. Morespecifically, the thermal oxidation process is executed at a temperatureranging from 950 to 1100° C. for a time period ranging 20 to 60 secondsunder the atmosphere of oxygen. The amorphous silicon layers 4 and 9 arepolycrystallized in the aforesaid process. Furthermore, the sides of theamorphous silicon layers 4 and 9 are oxidated in the aforesaid process.A degree of oxidation progress differs depending upon difference in thedopant (P) concentration in the oxidation. The amorphous silicon layers4 and 9 include vertically intermediate portions having thepredetermined dopant (P) concentrations respectively. The intermediateportions (regions designated by reference symbols 4 d and 9 d in FIG. 7)of the amorphous silicon layers 4 and 9 have maximum oxidated filmthicknesses respectively. The oxidated film thicknesses are reduced asthe amorphous silicon layers approach the upper and lower ends. Thesilicon oxide films are thus formed.

Subsequently, the silicon oxide films formed on the sidewalls of thefloating and control gate electrodes FG and CG are selectively removedby an etching process with the use of the chemical solution, as shown inFIG. 8. As the result of this process, the recesses 11 and 12 are formedin the sides of the control and floating gate electrodes 9 and 4 of thesides of the gate electrodes MG (that is, the sides of the word lines),respectively. Each of the recesses 11 and 12 has a generally shallowconfiguration and has a vertically deep intermediate portion and bothshallower upper and lower ends. In other words, each gate electrode MGis formed so that vertically intermediate portions of the control andfloating gate electrodes 9 and 4 have respective smaller gate widthsthan the upper and lower ends. When the recesses 11 and 12 are formed inthe control and floating gate electrodes 9 and 4 of each gate electrodeMG respectively, the distance between adjacent gate electrodes becomesmaximum near the center of each electrode and is gradually reduced aseach electrode approaches each of respective both ends.

Subsequently, the silicon oxide films 7 are formed between the adjacentgate electrodes MG (that is, the word lines) by the LPCVD method asshown in FIG. 9. In this case, tetraethoxysilane (TEOS) is supplied byan amount ranging from 100 to 1000 sccm at a temperature ranging from600 to 700° C., so that the silicon oxide films 7 are buried in spacesbetween the adjacent gate electrodes MG respectively. In the process,since each silicon oxide film 7 is formed uniformly along the adjacentsides of the gate electrodes MG, voids or air gaps 8 are finally formedin portions of each silicon oxide film 7 corresponding to the respectiverecesses 11 and 12.

Subsequently, as shown in FIG. 10, each silicon oxide film 7 between theadjacent gate electrodes MG is partially removed, and the siliconnitride film 10 for the forming of the hard mask is also removed. Next,a metal film 13 is formed on the polycrystalline silicon layers 9 andthe silicon oxide films 7 by sputtering as shown in FIG. 11. In thiscase, a metal such as Co, Ni, Ru or W is used as the metal film 13.Subsequently, the metal film 13 and the polycrystalline silicon layer 9are combined with each other by heat treatment, whereby the metalsilicide films 6 (see FIG. 3) for the control gate electrodes CG areformed. Thereafter, a metal stripping treatment is carried out to stripoff an unreacted metal film 13. As a result, the configuration as shownin FIG. 3 is obtained.

According to the foregoing embodiment, the forming of the recesses 11and 12 on the sides of the adjacent gate electrodes MG reliably resultsin the void in which no silicon oxide film 7 is present between theadjacent gate electrodes MG or the air gap in which no silicon oxidefilm 7 is buried. Consequently, the capacity between the adjacent memorycells between the gate electrodes MG can effectively be suppressed.Accordingly, a failure in data write or data readout can be preventedwhen data is written onto or read out of the memory cell. Particularlyin the foregoing embodiment, the air gaps 8 having different depths,horizontal size and the like can be formed by suitably adjusting the Pconcentration profiles of the amorphous silicon layers 9 and 4.

The present invention should not be limited by the foregoing embodiment.The embodiment may be modified or expanded as follows. In the foregoingembodiment, the difference in the phosphor (P) concentration is providedbetween the amorphous silicon layers 4 and 9 when the recesses 11 and 12are formed in the sides of each word line WL. The formed silicon oxidefilm is removed by the etching process with the use of the chemicalsolution while the difference in the oxidation speeds based on thedifference in phosphor concentration is utilized, whereupon the recesses11 and 12 are formed. However, the phosphor concentration difference maybe provided between the amorphous silicon layers 4 and 9, and therecesses 11 and 12 may be formed by utilizing the difference in dryetching speeds based on the phosphor concentration difference.

More specifically, the steps up to the provision of the P concentrationdifference as shown in FIGS. 4 to 6 are the same as those in theforegoing embodiment. Subsequently, a dry etching process is carried outwhile the sides of the gate electrodes MG are exposed (in the state asshown in FIG. 6). In this case, the dry etching is carried out with theuse of an octafluorobutene (C₄F₈) gas under the condition that a higherselectivity is given to the silicon substrate. In this process, a degreeof progress in the dry etching differs between the amorphous siliconlayers 9 and 4 for the forming of the control and gate electrodes CG andFG respectively depending upon difference in the internal Pconcentration between the layers. Accordingly, a region with higher Pconcentration is selectively dry etched, so that the configuration asshown in FIG. 8 is obtained. Subsequent steps (FIGS. 9-11 and 3) are thesame as those as described above. As a result, the modified formachieves substantially the same effect as the foregoing embodiment.

Additionally, the invention should not be limited to the NAND flashmemory but may be applied to NOR, AND and other types of nonvolatilesemiconductor devices.

The foregoing description and drawings are merely illustrative of theprinciples of the present invention and are not to be construed in alimiting sense. Various changes and modifications will become apparentto those of ordinary skill in the art. All such changes andmodifications are seen to fall within the scope of the invention asdefined by the appended claims.

1. A method of fabricating a semiconductor device, comprising: forming a gate insulating film on a semiconductor substrate; forming a first conductive layer, as a floating gate electrode, on the gate insulating film so that a vertically intermediate portion of the first conductive layer has a higher dopant concentration than vertically upper and lower portions of the first conductive layer; forming an intergate insulating film on the first conductive layer; forming a second conductive layer, as a control gate electrode, on the intergate insulating film so that a vertically intermediate portion of the second conductive layer has a higher dopant concentration than vertically upper and lower portions of the second conductive layer; dividing the first and second conductive layers and the intergate insulating film with a mask pattern formed on the second conductive layer serving as a pattern, thereby forming a plurality of gate electrodes; forming a first recess on a first side wall of the first conductive layer and a second recess on a second side wall of the second conductive layer with side surfaces of the gate electrodes being exposed; and burying insulating films between the gate electrodes respectively and forming a first and a second air gap portions in portions of the buried insulating films corresponding to the first and the second recesses respectively.
 2. The method according to claim 1, wherein the first conductive layer includes a first polycrystalline silicon layer and the second conductive layer includes a second polycrystalline silicon layer.
 3. The method according to claim 2, wherein the dopant introduced into the first and second polycrystalline silicon layers is phosphor (P).
 4. The method according to claim 1, wherein the first recess is formed from an upper edge portion to a bottom edge portion of the first side wall and the second recess is formed from an upper edge portion to a lower edge portion of the second side wall.
 5. The method according to claim 1, wherein the first and the second recesses forming step includes a step of forming a first oxide film on the first side wall and a second oxide film on the second side wall by a thermal oxidation treatment, and a step of selectively removing the first and the second oxide films with use of a chemical solution.
 6. The method according to claim 5, wherein the first oxide film is formed from an upper edge portion to the lower edge portion of the first side wall and the second oxide film is formed from an upper edge portion to the lower edge portion of the second side wall.
 7. The method according to claim 6, wherein a thickness of a middle portion of the first oxide film is larger than a thickness of an edge portion of the first oxide film.
 8. The method according to claim 1, wherein the first and the second recesses forming step includes a step of etching the first and the second side walls by reactive ion etching (RIE) method.
 9. A method of fabricating a semiconductor device, comprising: forming a gate insulating film on a semiconductor substrate; forming a first conductive layer on the gate insulating film by forming a first undoped amorphous silicon layer on the gate insulating film, forming a first amorphous silicon layer doped with phosphor on the first undoped amorphous silicon layer and forming a second undoped amorphous silicon layer on the first amorphous silicon layer; forming an intergate insulating film on the first conductive layer; forming a second conductive layer on the intergate insulating film by forming a third undoped amorphous silicon layer on the intergate insulating film, forming a second amorphous silicon layer doped with phosphor on the third undoped amorphous silicon layer and forming a fourth undoped amorphous silicon layer on the second amorphous silicon layer; dividing the first and second conductive layers and the intergate insulating film with a mask pattern formed on the second conductive layer serving as a pattern, thereby forming a plurality of gate electrodes; forming a first recess on a first side wall of the first conductive layer and a second recess on a second side wall of the second conductive layer with side surfaces of the gate electrodes being exposed; and burying insulating films between the gate electrodes respectively and forming a first and a second air gap portions in portions of the buried insulating films corresponding to the first and the second recesses respectively.
 10. The method according to claim 9, wherein the first recess is formed from an upper edge portion to a bottom edge portion of the first side wall and the second recess is formed from an upper edge portion to a lower edge portion of the second side wall.
 11. The method according to claim 9, wherein the first and the second recesses forming step includes a step of forming a first oxide film on the first side wall and a second oxide film on the second side wall by a thermal oxidation treatment, and a step of selectively removing the first and the second oxide films with use of a chemical solution.
 12. The method according to claim 11, wherein the first oxide film is formed from an upper edge portion to the lower edge portion of the first side wall and the second oxide film is formed from an upper edge portion to the lower edge portion of the second side wall.
 13. The method according to claim 12, wherein a thickness of a middle portion between the upper and the lower edge portions of the first oxide film is larger than a thickness of the upper and the lower edge portions of the first oxide film and a thickness of a middle portion between the upper and the lower edge portions of the second oxide film is larger than a thickness of the upper and the lower edge portion of the second oxide film.
 14. The method according to claim 9, wherein the first and the second recesses forming step includes a step of etching the first and the second side walls by reactive ion etching (RIE) method.
 15. A semiconductor device comprising: a semiconductor substrate; a gate insulating film formed on an upper surface of the semiconductor substrate; a plurality of gate electrodes including a floating gate electrode formed on the gate insulating film, an intergate insulating film formed on the floating gate electrode, and a control gate electrode formed on the intergate insulating film; and a plurality of inter-electrode insulating films formed on portions of the semiconductor substrate located between the gate electrodes, wherein each floating gate electrode has a pair of first vertical end portions and a first vertically intermediate portion between the first vertical end portions, the first vertically intermediate portion has a first gate width which is smaller than a second gate width of the first vertical end portions, and each control gate electrode has a pair of second vertical end portions and a second vertically intermediate portion between the second vertical end portions, the second vertically intermediate portion has a third gate width which is smaller than a fourth gate width of the second vertical end portions, and each inter-electrode insulating film has a first air gap portion corresponding to the first vertically intermediate portions of the floating and the control gate electrodes and a second air gap portion corresponding to the second vertically intermediate portions of the floating and the control gate electrodes.
 16. The device according to claim 15, wherein the floating gate electrode includes a first polycrystalline silicon layer and the control gate electrode includes a second polycrystalline silicon layer.
 17. The device according to claim 16, wherein the first and the second polycrystalline silicon layers include a vertical upper end portion, a vertical lower end portion and a vertical middle portion between the vertical upper and lower end portions, respectively, a dopant concentration of the vertical middle portion of the first and the second polycrystalline silicon layers is higher than a dopant concentration of the vertical upper and lower end portions of the first and the second polycrystalline silicon layers.
 18. The device according to claim 15, wherein a first side wall of the floating gate electrode includes a first recess and a second side wall of the control gate electrode includes a second recess.
 19. The device according to claim 18, wherein the first recess is formed from an upper end portion to a lower end portion of the first side wall and the second recess is formed from an upper end portion to a lower end portion of the second side wall.
 20. The device according to claim 18, wherein the first recess is formed at the whole first side wall and the second recess is formed at the whole second side wall. 